The present invention in one embodiment relates to semiconductor processing methods, and particularly to methods for forming trenches having different widths and the same depth.
Trenches are widely used in semiconductor technology to form patterned structures. For example, contact vias and interconnect lines in metal interconnect structures are formed first by forming trenches in a dielectric material layer that provides electrical insulation among conductive structures, followed by filling the trenches with a conductive material to form additional conductive structures. Further, shallow trench isolation structures are formed by forming trenches in a semiconductor substrate, followed by filling the trenches with a dielectric material to provide electrical isolation between adjoining semiconductor regions.
In general, trenches refer to any recessed structure from a top surface, which is typically planar. The depth of each trench is typically affected by the surrounding structures around each recessed structure because of an inherent processing feature of an etch process employed to form the trenches. Specifically, a reactive ion etch (RIE) which is typically employed to form trenches has the undesirable feature of pattern factor dependency of the profile and the depth of the trenches. This phenomenon is also known as a RIE lag. The pattern factor dependency arises due to the nature of the reactive ion etch, which employs a finite supply of reactive ions, and consequently, limits the reaction rate by the supply of the reactant. Thus, a trench surrounded by a large unpatterned region (non-etched region) typically has a greater depth than a trench surrounded by a patterned region (etched region).
The pattern factor dependency of the depth of trenches is typically amplified by the etch residues, which may be polymers from a photoresist employed to form a pattern over the material layer in which the trenches are formed. As the etch residue is deposited on, or flows down onto, the sidewalls of the trenches, the etch residue tends to prevent the etching of the portions of the material layer covered by the etch residue.
Thus, in the prior art, the isolated trench extends to a different depth than the nested trenches. Typically, wide isolated trenches extend to deeper depth than nested trenches. The conductive structure formed by filling the isolated trench, therefore, has a greater capacitive coupling with the metal interconnect structures as well as greater probability of having an electrical short with the metal interconnect structures. The increase in the capacitive coupling increases the RC delay time for the conductive structure, adversely impacting the performance of a semiconductor chip. The increase in the probability of an electrical short reduces the chip yield, lowering the productivity of the manufacturing process. Thus, the conventional reactive etch process provides adverse effects in terms of performance and productivity through the structural characteristics.